In memory devices, control circuitry is used to interpret user commands and activate relevant peripheral circuits which perform, in respect of the memory, the user commands. Usually a single user command requires a defined sequence of events to be performed. The control circuitry acts as a state machine to provide a coded signal or state for each stage of the sequence of events. A state machine provides a set of states and a set of transition rules for moving between those states at clock edges. In order to activate the relevant peripheral circuits, the control circuitry has to send the coded signals to these circuits. A control bus can be thus provided which is routed throughout the memory device. Each peripheral device is provided with a decoder which activates the respective peripheral circuit when a valid state from the bus is decoded.
If a chip malfunctions, it is desirable to know whether the malfunction is caused by a fault in the control circuitry or in one of the peripheral circuits. Some known arrangements incorporate dedicated local test circuitry which can be activated by a tester. Each peripheral circuit would be provided with its own test circuitry to test whether or not the peripheral circuit is functioning correctly. Circuitry is also provided to connect test inputs of the circuit to the test circuitry of each peripheral circuit. This considerably increases the amount of circuitry required which is undesirable.
As an alternative solution, the controlling input of the peripheral circuit to be tested can be probed by a microprober which forces that input to an active state. In this way, it can be seen whether or not the peripheral circuit is functioning correctly. However, this solution is only really feasible if the controlling input of the circuit to be tested is readily accessible. Often the inputs of such circuits are not readily accessible and thus the peripheral circuit cannot be readily tested. It can also be difficult to force the voltage with a microprober even if the input is accessible. This is a consequence of the smaller geometries present on modem integrated circuits.